by Jim Harrison
The IEEE International Electron Devices Meeting begins on Monday (10 Dec. 2012) at the Hilton Hotel in San Francisco. There are 33 sessions taking place through Wednesday afternoon.
One of the papers that caught my eye is a part of session 8: Nano Device Technology – Ultimate CMOS Devices – on Tuesday, December 11, starting at 9:00 am. The researcher will discuss a FET with the ability to switch between N- or P-type.
8.4 10:20 a.m. Tuesday. Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs, M. De Marchi, D. Sacchetto, S. Frache, J. Zhang, P.-E. Gaillardon, Y. Leblebici, G. De Micheli, EPFL
We fabricated and characterized ambipolar Silicon Nanowire (SiNW) FET transistors featuring two independent Gate-All-Around (GAA) electrodes and vertically stacked SiNW channels. One of the gate electrodes is exploited to dynamically select the polarity of the devices (n or p-type).
Measurement results on silicon show Ion/Ioff > 106 and S≈64mV/dec (70mV/dec) for p-type and n-type operation in the same device. We show that XOR operation is embedded in the device characteristic, and we implement for the first time a fully functional 2-transistor XOR gate to demonstrate the potential of this technology for logic circuit design.
Ambipolar Nanowire FETs: The phenomenon of ambipolar conduction (ability to switch between N- or P-type) has been observed in some nanoscale transistors made from silicon, carbon and graphene. While it is typically considered a limitation for circuit design at the 22nm node and below, a team led by researchers from the Swiss Federal Institute of Technology in Lausanne (EPFL) decided to try to exploit this property. They built gate-all-around ambipolar Si nanowire FETs in a vertically stacked configuration on an SOI substrate. A “polarity gate” attached to the ends of the nanowires is used to switch their polarity dynamically between the N and P states, while a control gate in the middle turns them on or off. The researchers built a logic gate (the XOR function) to show the technique’s usefulness for future logic design.