by Jim Harrison
If you’re headed to the InterSolar conference you better be sure to pre-register. The registration area was a very busy place on Tuesday. Many booths in the exhibit area were also humming – there are about 900 total exhibitors with everything from solar panels and solar inverters, to mounting systems and analysis software. The many technical sessions and keynote presentations were very well attended.
One popular topic of conversation was solar storage – using very large Li-ion batteries in a utility-scale solar electric power system to buffer and smooth energy output and to take over during outages.
The SemCon show floor was also a busy place. There was a lot of talk about Intel’s investment of $2.1B in Dutch chip-equipment maker ASM Lithography. ASML provides the extremely complex lithography equipment needed to squish a few more million transistors onto a silicon wafer – something Intel is always very keen to do. In order to get to feature sizes much smaller than the current 22 nm the chip makers will probably need extreme ultraviolet lithography (EUV), rather than 193-nm UV light (ArF) that is state of the current art.
Wafer manufacturer Soitec, and chip maker STMicroelectronics were talking a lot about alternatives to FinFET chip technology. Fully-depleted Silicon-on-Insulator (FD-SOI) planer chips may be easier to manufacture while providing the low gate leakage need with 22 nm and below process technology.
Meanwhile, IMEC (Leuven, Belgium) is building a clean room facility for handling huge 450 mm wafers – moving up from the current state-of-the-art 300 mm silicon size to make transistors even cheaper.
IMEC also discussed an available and production ready crystalline Si solar cell technology with 20% efficiency using their proprietary PERC process. This uses a large-area (125 x 125 mm²) Cz p-type silicon cell with a simple homogeneous emitter and Ag-single screen-printed front side contacts (65 µm finger width), two bus-bars and an adapted Al back-side metallization.