EEbeat

Samsung Electronics and Cadence have teamed up to deliver a 20-nm design methodology that incorporates double patterning technology for joint customer deployment and internal test chips. The collaboration between these two companies brings new process advances for mobile consumer electronics, enabling design at 20 nm and future process nodes.

Double patterning is a new approach to lithography which allows higher routing density for advanced process nodes. It splits each metal layer of designs into two masks for chip fabrication, enabling higher metal density and smaller silicon area for process technologies at 20-nanometers and below.

At this time the Cadence® Encounter® RTL-to-GDSII flow, Virtuoso® custom/analog flow, and Cadence signoff solutions were qualified for and deployed with Samsung’s 20-nm fabrication process.

For the digital parts of the chip, the Encounter Digital Implementation (EDI) System provided an automated methodology for double patterning-correct placement and routing using its patent-pending FlexColor technology for real-time colorization. The EDI System delivers die-area efficiency and DRC accuracy during placement, optimization and routing. For final signoff, engineers used the Cadence Encounter Timing System, Encounter Power System and QRC Extraction, which has been enhanced to accept multiple extraction values to manage variation in double-patterning alignment.