Like all microcontroller (MCU) vendors, Renesas offers comprehensive hardware and software manuals for its products. And a design team will need those detailed guides at some point. But a new Quick Design Guide for the RX610. RX62N, and RX621 MCU families can provide quicker answers to many questions than can the detailed manuals. Moreover the new Guide offers application advice as well.
The Guide starts with basics such as power-supply circuits, MCU operating modes, the flexibility to support big- or little-endian operations, and clock and reset circuits. And it continues through details in terms of memory maps and the variety of sleep modes that ensure an optimum mix of power consumption and performance.
For example, let’s consider the memory map in this post and perhaps we’ll review other sections down the road. The image below details the memory map.
All of the RX family MCUs have a 32-bit memory space totaling 4 Gbytes. The space includes support for on- and off-chip memory, and memory-mapped I/O for peripherals.
We covered the bus structure used in the RX early on in the Doctor Micro blog – describing how the MCU dedicates separate buses for instructions and data in an enhanced Harvard architecture. But the instruction and data share the same address space with the memory map allocating regions for each ensuring that the MCU can access instructions and data on each cycle.
All members of the RX family include RAM that can be accessed in a single cycle at clock speeds up to 100-MHz. The maximum RAM array is 128 kbytes in size and it is located at the bottom of the memory map.
The architecture allocates separate Flash memory sections for program and data storage. Each is optimized for the task at hand. The program memory that Renesas calls ROM, but that is erasable, is located at the top of the memory map. The ROM array can be rewritten with a granularity of 256 bytes to support field updates, but is optimized for the read operations that feed the processor. Indeed as we covered previously, the processor can access the program store at speeds to 100 MHz without incurring wait states.
The data Flash area occupies a space as large as 32 kbytes in the middle of the memory map. That memory can be rewritten with a granularity of 8 bytes – optimized for usages such as storage of configuration parameters.
Much of the rest of the memory map will be dictated by the specific RX MCU. For instance some include an SDRAM controller for external memory. And programmable chip selects allow the design team great flexibility in interfacing the RX to external devices.
Remember that one of the best opportunities to learn about using the RX is around the corner at the Renesas DevCon scheduled for October 11-14 in Orange County, CA. I summarized the RX-centric sessions in a prior post.