I’ve written twice recently on interrupt response and the advantages of the Renesas RX microcontroller (MCU) architecture in that area. I detailed how the application engineering team measured a typical interrupt response of 7 CPU clock cycles. Now let’s consider how you can get even quicker response if you have a specific need in your application for fast interrupt service. The RX includes a Fast Interrupt Function that can be utilized with one interrupt source. Moreover the large register file in the RX can slice time in the interrupt service routine (ISR).
In the case of a standard interrupt, the RX must store the contents of the program counter (PC) and processors status word (PSW) and then fetch an interrupt vector from memory before entering the ISR. That’s a typical scenario for most MCUs and microprocessors.
The RX, however, includes three additional 32-bit registers in hardware that can accelerate interrupt response from one source that’s determined by the programmer. The registers are the BPC (Backup PC), BPSW (Backup PSW), and the FINTV (Fast Interrupt Vector Register). When the designated fast interrupt occurs, the MCU can store the PC and PSW to the backup registers and read the interrupt vector from the FINTV register.
While the RX offers zero-wait-state access to Flash memory, the hardware registers can be written and read more quickly. The RX application engineers repeated the same test that I described in the prior post that’s linked above, but with the timer interrupt designated as the fast interrupt.
The instruction in the ISR that read the timer value measured only 12 CPU clock cycles in the case of the fast interrupt – two cycles faster than the standard interrupt. The ISR was identical to the one that described in the prior case. So subtracting the 8 cycles in the ISR we get an interrupt response of 4 clock cycles. Or as I stated in another earlier post on interrupts, the processor issues the first instruction in the ISR on the 5th clock cycle after the interrupt.
Now the time spent in the ISR matters as well. So programmers have the further ability to trim response time there as well.
The programmer can choose to dedicate three of the general-purpose registers (R10-R13) to interrupt processing. That’s not a realistic option on most MCUs that have only eight general-purpose registers, but is certainly viable on the RX with 16 registers.
When the application engineers generated the code for the interrupt test with dedicated registers, the push instruction we discussed previously was no longer the first instruction in the ISR. There is no reason to save the registers to the stack as long as the ISR can execute with just the three dedicated registers. So the first two instructions in the ISR were the move (MOV) instruction we discussed previously with the timer being read by the second of the MOV instructions.
The dedicated registers trimmed the time between the interrupt and the timer read to 10 CPU clock cycles or 100 nsecs – an aggregate savings of four clock cycles when using both the fast interrupt and dedicated register options.
We still have more to discuss about interrupts. There’s the issue of exiting the ISR that comes into play, and we’ll also discuss external interrupts in a future post.