EEbeat

There really is a lot to learn about the Renesas RX microcontroller (MCU) architecture – especially to understand the advantages it affords in code size, performance, math capabilities, and data movement. A new narrated RX presentation on the Renesas site offers an excellent way to get a quick (less than a half hour) and comprehensive introduction. The presentation addresses many of the things we covered in this blog and some that we haven’t.

I’ll highlight a few points made in the presentation. I’d highly recommend that you view the presentation if you work with MCUs.

The RX features a unique microarchitecture designed by Renesas and that is a competitive advantage since the design team was able to implement the best of RISC and CISC architectures. Moreover, Renesas developed the 90-nm MONOS (metal oxide nitride oxide silicon) Flash cell that delivers zero-wait-state operation and a decided performance advantage over competitive architectures such as those from ARM.

Both an integrated floating-point unit (FPU) and multiplier hardware afford the RX superior math capabilities. The architecture can handle a 32-bit multiply instruction in a single cycle. The FPU can access general purpose registers whereas RISC MCUs require load and store operations to special FPU registers. The design can take on DSP or digital signal controller (DSC) applications.

Early on in this blog, I covered the five buses in the RX that allow simultaneous data movement for multiple operations. The presentation covers an example in which the MCU performs three parallel operations simultaneously:

• The CPU executes instructions from Flash memory
• The integrated ADC transfers data to SRAM
• The External DMA controller transfers data to an LCD controller.

 The architecture allows the RX to accomplish more than even a performance benchmark might reveal. In the example above, the External DMA controller can move frame buffer data from external memory to the LCD and support a 60-Hz screen refresh rate. That operation places only a 5% load on the CPU freeing it for other tasks.

 There is also excellent discussion on several slides focused on the CISC architecture and features such as the flexible addressing modes available to compilers and programmers. I have covered that flexibility before such as in a post on the MOV (move) instruction. But the presentation makes a simple but powerful comparison that I’ll share.

 Consider the simple task of moving data from one memory location to another. A RISC processor must use a pair of load and store operations to move the data. The operation requires 4 CPU cycles and 4 bytes to encode the instructions. The RX MOV instruction accomplished the same task in 3 CPU cycles and requires only 2 bytes to encode the instruction. That’s a performance and code-density advantage.

 The presentation also does a great job of summarizing all of the available RX-family MCUs including those available with an extended temperature range. And you’ll get a good look at the product roadmap planned in the next couple of years.

This blog post was originally published on the Renesas Rulz Doctor Micro blog.