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Any number of microcontroller (MCU) applications require fast response to internal and external interrupts. For example, real-time control applications such as motor control require immediate response to internal MCU peripherals such as timers and external events such as user controls. The Renesas RX MCU architecture offers interrupt response that meets the most demanding of applications and includes an architectural feature called a fast interrupt function that can further accelerate response to a specified internal or external interrupt source.

 The interrupt subject is a complex one that I will address over a series of blog posts in the coming weeks. I’d like to lay groundwork for future posts today.

 First of all, it’s important to recognize that a number of factors impact interrupt response time. There is the inherent time the MCU architecture takes to recognize an interrupt and transfer control to the interrupt handler or interrupt service routine (ISR).

 Memory access speed also comes into play. One of my first posts here addressed Flash memory access speeds. Because the RX family integrates zero-wait-state Flash memory at clock speeds up to 100 MHz, embedded design teams can accurately determine worst-case interrupt response time. For MCUs that incur wait states on memory accesses, a best-case interrupt response time isn’t necessarily a realistic interrupt response time. When the CPU clock frequency exceeds the speed at which zero-wait-state operation is possible, the actual interrupt response time can escalate by a factor of 2, 3 or more.

 There are also architectural issues that impact how well the code in the ISR performs – or more succinctly how quickly the routine addresses the reason for the interrupt. The depth of the pipeline impacts the amount of time it takes to do meaningful work in the ISR. The first instruction in an ISR takes multiple cycles to execute – but the pipeline fills during that delay allowing subsequent instructions to execute normally.

 In general, the RX architecture responds to an interrupt in 7 clock cycles. The first instruction in the ISR is issued on the 7^th cycle after the interrupt is detected. The fast interrupt response function can speed the response so that the first instruction is issued on the 5^th cycle. Moreover, the architecture offers the option of dedicating some registers to the fast interrupt function and that can save cycles in the ISR.

 The RX interrupt performance is significantly better than competitive MCUs. For instance, the ARM Cotex-M3 typically responds in 12 cycles although the response is significantly slower when the CPU clock speed exceeds the Flash access speed. The ARM7 and MIPS M4K architectures are slower still in interrupt response time.

 In future posts, I will provide a detailed look at how to measure interrupt response and on how the fast interrupt function works.

 This post was originally published on the Renesas Rulz Doctor Micro blog.

Maury Wright