Maybe it’s because of my odd sense of humor, or that I like to read Dilbert and The Far Side comics, but I have this picture in my head of a poor down-trodden test engineer on a street corner with a scribbled cardboard sign that reads, “Can you spare some pins?” I know this image is far-fetched, but according to the things I read and the people I talk to, the trend of fewer IC pins available for digital manufacturing test is real. And, as a result, the poor test engineer needs to figure out how to maintain high test quality with less.
It’s ironic that new IC designs can contain millions or tens of millions of gates and continue to grow, yet the number of I/O pins on the external interface remains the same or is shrinking in some cases. From a test perspective, there is more to test with fewer control and observation points to do it with. Similar to how these systems on a chip (SoC) designs incorporate on-chip clocks and other functionality to reduce the external interface, test techniques that include on-chip logic to minimize the number of pins are also required to interface with the external automated test equipment (ATE).
Some of the reasons for the reduced number of digital test pins include:
- Packaging issues and the costs of additional pins.
- Reduced ATE interface, either for test pins or the functional I/O pins, or both. This can be for actual tester hardware limitations or in an effort to use less expensive (and capable) testers.
- Multi-site testing, that is, testing multiple devices in parallel.
- Wafer test and the goal to minimize the contact points per die.
- Growing analog design content.
- Use of more high-speed serial pins to transfer parallel data over serial streams.
More and more, IC design companies are dealing with one or more of these reasons for fewer test pins and need help to implement a good digital test within these limitations.
There are two terms I have commonly seen to describe the different test techniques I’ll outline below. The first is reduced pin-count test (RCPT) and the second is low pin-count test (LPCT). The RPCT approach is a methodology that uses existing boundary scan logic to reduce the number of functional pins that interface to the ATE during scan test.
Boundary scan logic is prevalent in ICs today. Boundary scan refers to the IEEE 1149.1 standard that adds some hardware on the device around the boundary of the chip. Each pin pad is connected to a special boundary scan cell, and they are stitched together into a boundary scan chain. The logic is controlled by a state machine, and the external interface is called a test access port (TAP) with either four or five pins total. The 1149.1 standard was originally created to test the circuit board interconnections between ICs, but since then, additional test techniques have taken advantage of this existing test interface.
If special RPCT boundary scan cells are used on the functional pins where test values are normally supplied or captured during scan test, the TAP interface and boundary scan chain can be used to control and observe those values instead of hooking up all those pins to the ATE. This approach results in a large reduction in the number of test pins needed while keeping the test quality the same. The technique works for both stuck-at and at-speed transition scan patterns.
Another use of the TAP interface is for controlling on-chip built-in self-test (BIST) logic. BIST logic is usually added to designs to test the internal memories and sometimes it is also used for testing digital logic blocks or modules. These are referred to as MBIST and LBIST respectively. The BIST controllers reside on-chip and interface to the memories or logic they are designed to test. The BIST approach eliminates the storing of test patterns on ATE because the whole test is contained within the device. The TAP controller can be designed with some custom instructions and registers to control the BIST tests and capture the test results. If the TAP interface was not used for the BIST control, the BIST controllers would need separate external pin access to the ATE.
The most common manufacturing test technique for digital logic is to use scan patterns created by an automatic test pattern generation (ATPG) tool. This technique replaces the design’s flip-flops with scan cells and stitches them into scan chains. The scan chains connect directly to scan channels on the ATE pin interface for shifting in test patterns and shifting out the captured test responses for comparison with expected results. To reduce scan test pattern volume and test application time, on-chip test compression has grown considerably over the past seven years or so all across the chip design industry.
The term LPCT refers to using the on-chip test compression logic to also significantly reduce the number of ATE pins needed to provide the test patterns. The on-chip compression logic interfaces the ATE scan channels to the internal scan chains, but the relationship is one-to-many instead of traditional ATPG’s one-to-one configuration. This allows the tester interface pin count to be very low, even down to one scan channel per design, or one per block if it is used in a modular fashion. I have seen this technique successfully used many times on industry designs.
There are different on-chip compression solutions available. It is best to use one that compresses both the test time and data volume. Some solutions can reduce the number of pins needed, but compromise the test time compression by using a technique like a serial to parallel converter to lower the pin count requirements.
If lowering the number of test pins required for your designs is important to you or your company, I encourage you to consider implementing one or more of the approaches outlined here. All of them have proven to provide high quality test while also reducing the tester interface needs. I just had another thought as I noticed the stuffed Dogbert toy on my desk that I got at the Design Automation Conference years ago — I think I will add Dogbert into the image in my mind of the cardboard-holding test engineer. She or he might not get any more pins, but at least they would have a companion.
by Bruce Swanson
About the Author:
Bruce Swanson is a Technical Marketing Engineer in the Silicon Test division at Mentor Graphics. He received an MS in applied information management from the University of Oregon and a BS in computer engineering from North Dakota State University. Bruce has over 20 years of experience in EDA and computer hardware design.